DP-HLS: A High-Level Synthesis Framework for Accelerating Dynamic Programming Algorithms in Bioinformatics
IEEE International Symposium on High-Performance Computer Architecture (HPCA), Sydney, Australia, Feb 2026.
— One of the top-4 computer architecture conferences (alongside ISCA, MICRO, ASPLOS);
~75 papers accepted out of 410 submissions in 2024 (18.3% acceptance rate).
Abstract
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Dynamic programming (DP) based algorithms are essential yet compute-intensive parts of numerous bioinformatics pipelines. This paper introduces DP-HLS, a novel framework based on High-Level Synthesis (HLS) that simplifies and accelerates the development of a broad set of bioinformatically relevant DP algorithms in hardware. DP-HLS features an easy-to-use template with integrated HLS directives, enabling efficient hardware solutions without requiring hardware design knowledge. We implemented 15 diverse DP kernels, achieving 1.3–32× improved throughput over state-of-the-art GPU and CPU baselines.