Curriculum Vitae

General Information

Summary

• As a computer science researcher specializing in computational genomics, I am dedicated to advancing the field through the development of optimized hardware+software accelerated tools. My work addresses critical computational bottlenecks at the exciting intersection of computational genomics and computer engineering.
• My research focuses on devising fully automated and scalable methods to accelerate error-prone phylogenetic estimation techniques. By doing so, we aim to contribute significantly to evolutionary biology studies and help unravel the complexities of the tree of life.
• In parallel, we are developing an HLS-based framework to accelerate dynamic programming-based algorithms used in bioinformatics on FPGA. This project aims to help bioinformaticians customize their algorithms and port on FPGA efficiently with less effort.

Education

2022 - Present

University of California San Diego – Ph.D. in Computer Science and Engineering

• Location: La Jolla, California, USA
• Advised by: Prof. Yatish Turakhia
• Research exam: Accurate, scalable, and fully automated inference of species trees with raw genomic assemblies using ROADIES
• Research exam committee: Prof. Sanjoy Dasgupta, Prof. Nuno Bandeira, Prof. Melissa Gymrek

2022 - 2024

University of California San Diego – M.S. in Computer Science and Engineering

• Location: La Jolla, California, USA
• Advised by: Prof. Yatish Turakhia
• GPA: 4.0 (4.0 scale)
• Master’s degree requirements completed while working towards Ph.D.

2019 - 2022

Indian Institute of Engineering Science and Technology Shibpur – Bachelor of Technology in Electronics and Telecommunication Engineering

• Location: Howrah, West Bengal, India
• Advised by: Prof. Ankita Pramanik
• Grade: 9.55 (10 scale)
• 4^th out of 78 students

Work Experience

June 2023 - Sep 2023

ASIC BU Digital Design Intern at Analog Devices, Inc.

• Location: Wilmington, Massachusetts, USA
• Conducted architectural benchmarking for Cadence Tensilica Xtensa configurable processors.
• Characterized performance, power, and area metrics for optimal low-power embedded processor configurations.

July 2019 - August 2022

Digital Design Engineer at Analog Devices, Inc.

• Location: Bengaluru, India
• Optimized radar signal processing algorithms for automotive radar-based SoC, reducing DSP cycle count by 33% with SIMD operations.
• Contributed to the digital front-end design and tape-out of 16V Li-ion Battery Management Systems (BMS) SoC.
• Conducted quality assurance tasks (Lint, Clock/Reset Domain Crossing (CDC/RDC), Logic Equivalence Checks (LEC)) for BMS SoC RTL design, ensuring design integrity.
• Evaluated ARM Cortex-M processor architecture and SRAM/ROM architecture for low-power embedded SoCs.

Other Research Experience

May 2018 - July 2018

DAAD WISE Research Scholar at University of Bremen

• Location: Bremen, Germany
• Advised by: Prof. Rolf Drechsler
• Optimized fault-tolerant quantum circuits by reducing their synthesis cost using Clifford+T gate library.
• Achieved 10-50% reduction of T-gate count with same qubits, significantly optimizing synthesis costs.

Technical Skills

• Languages: Verilog, SystemVerilog, Python, C/C++, R, MATLAB, CUDA, Intel TBB, OpenCL.
• Tools and Frameworks: Git, Docker, Bash, Slurm, VS Code, RStudio, Amazon AWS, Snakemake, Xilinx Vitis HLS, Vivado Design Suite, Synopsys SpyGlass, Cadence SimVision.

Projects

• Optimization of HLS4ML Library

  • Improved HLS4ML library for efficient Machine Learning hardware inference via High-Level Synthesis.
  • Partnered with CERN’s HLS4ML development team, contributing to several key feature enhancements and optimizations.

• Parallelized Suffix Array Construction

  • Implemented CUDA-based Suffix Array construction, enhancing speed by 86-571x compared to CPU baseline.
  • Applied various parallelization and SIMD vectorization techniques with CUDA, optimizing Suffix Array efficiency.

• Parallelized Read Mapping Algorithms

  • Utilized Intel Thread Building Blocks for bioinformatics read mapping, achieving a significant speed boost.
  • Integrated CUDA in read mapping algorithms, streamlining genomic data processing.

• Matrix Multiplication Acceleration

  • Enhanced C-based matrix multiplication speed by implementing blocking and Intel AVX2 vectorization.
  • Improved CUDA matrix multiplication on K80 and T4 GPUs using blocking and shared memory techniques.
  • Optimized Aliev-Panfilov solver performance with C++ and MPI on the Expanse supercomputer, achieving significant computational efficiency gains.

• CPU Branch Predictor

  • Developed models for Gshare, Tournament, Perceptron and TAGE branch predictors in C, improving CPU prediction accuracy.
  • Designed L1 Cache with FIFO replacement, optimizing memory access and CPU performance.

Other Interests

• Hobbies: Travelling, Painting, Fine Arts