Curriculum Vitae

Last updated: Aug 2026

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Summary

PhD candidate in Computer Science and Engineering specializing in high-performance computing, hardware–software co-design, and accelerator systems for genomics and AI workloads. Experience spans GPU/CPU-parallel software, FPGA/HLS accelerator design, performance characterization, and more than three years of ASIC/SoC development, including chip tape-out. Author of research published in PNAS and HPCA.

Education
Sep 2022 – Present
University of California San Diego — La Jolla, CA
Ph.D. in Computer Science and Engineering  (M.S. awarded, GPA: 4.0)
Jul 2015 – May 2019
IIEST Shibpur — West Bengal, India
B.Tech. in Electronics and Telecommunication Engineering
Publications [Google Scholar]
DP-HLS: A High-Level Synthesis Framework for Accelerating Dynamic Programming Algorithms in Bioinformatics.
A. Gupta*, Y. Cao*, J. Liang, Y. Turakhia. IEEE HPCA 2026, Sydney, Australia. [paper]
Accurate, scalable, and fully automated inference of species trees from raw genome assemblies using ROADIES.
A. Gupta, S. Mirarab, Y. Turakhia. Proc. Natl. Acad. Sci. U.S.A. 122(19), e2500553122 (2025). Featured on journal cover. [paper]
Organ Detection in Surgical Videos Using Neural Networks.
A. Kumar, A. Gupta, A. Pramanik. SmartCom 2020. [paper]
T-depth Optimization for Fault-Tolerant Quantum Circuits.
P. Niemann, A. Gupta, R. Drechsler. IEEE ISMVL 2019. [paper]
Work Experience
Jun – Sep 2025
AMD Research & Advanced Development (RAD) — San Jose, CA
Research Associate – PhD  ·  Mentor: Stephen Neuendorffer
  • Emulated sub-modules of an advanced AI test chip on cutting-edge FPGA platform, contributing to hardware and software bring-up of custom silicon.
  • Conducted runtime performance characterization of AI models on the target test-chip architecture.
Jun – Sep 2023
Analog Devices, Inc. — Wilmington, MA
ASIC BU Digital Design Intern
  • Conducted hardware architectural benchmarking for Cadence Tensilica Xtensa configurable processors.
  • Characterized performance, power, and area metrics for low-power embedded processor configurations.
Jul 2019 – Jul 2022
Analog Devices India Pvt. Ltd. — Bengaluru, India
Digital Design Engineer
  • Optimized embedded signal processing kernels using SIMD operations and architecture-specific vectorization, reducing DSP cycle count by 33%.
  • Contributed to the digital front-end design and tape-out of a low-power Battery Management SoC.
  • Evaluated ARM Cortex-M processor and SRAM/ROM architecture power, performance, and area trade-offs for low-power embedded SoCs.
Research Experience Mentor: Prof. Yatish Turakhia
May 2025 – Ongoing
ML Hardware Acceleration
  • Designing hardware-aware weight compression techniques to optimize and accelerate deep learning inference on specialized hardware.
  • Focused on maximizing computational efficiency and reducing memory footprint for deploying large-scale neural networks at the edge.
Jan 2023 – Ongoing
ROADIES — Automated Species Tree Inference Tool
  • Led the development of ROADIES, a reference-free, GPU/CPU-parallelized HPC tool for evolutionary genomics.
  • Produces species trees comparable in quality to state-of-the-art approaches in substantially less time.
  • Published in PNAS 2025, featured on the journal cover. Presented at ISMB 2024.
  • Used by researchers beyond our group; 2K+ conda downloads, 43 GitHub stars.
Nov 2022 – Jun 2024
DP-HLS — FPGA Acceleration Framework
  • Co-developed DP-HLS, an HLS-based framework achieving 1.3–32× improved throughput over GPU/CPU baselines and ~20× faster implementation time for bioinformatics dynamic-programming algorithms.
  • Designed parameterizable systolic array architectures for easy algorithm customization without hardware redesign.
  • Published at IEEE HPCA 2026, Sydney, Australia.
Service
Artifact Evaluation Committee, ISCA 2025, ISCA 2024.
Reviewer, Bioinformatics (Oxford Academic), RECOMB 2026 (Satellite Workshop), MBE.
Workshop Co-organizer, BioSys Workshop @ ASPLOS 2024, San Diego, CA.
Technical Skills
GPU & HPC Acceleration CUDA, MPI, OpenMP, Intel TBB, Slurm, Amazon AWS, Snakemake, Conda, Bash
Programming Python, C/C++, R
Hardware & Co-Design ASIC/Custom Silicon Design Flow, FPGA (AMD/Xilinx), High-Level Synthesis (HLS, Vitis HLS), Vivado, Verilog, SystemVerilog
Other Projects
Jan 2023 – Mar 2024
Parallelized Genomic and HPC Algorithms  C++, CUDA, Intel TBB, Git
  • Parallelized Suffix Array construction on GPUs, achieving 86–571× speedup over optimized CPU baselines.
  • Accelerated dense matrix multiplication on NVIDIA K80/T4 GPUs; implemented Intel AVX2 vectorization.
  • Optimized large-scale solvers (Aliev-Panfilov) on the Expanse Supercomputer using MPI and C++.
Apr – Jun 2023
Optimization of HLS4ML Library  Vitis HLS, Vivado, Git, Python
  • Improved the HLS4ML library for efficient ML hardware inference via HLS, focusing on the DL-to-FPGA flow.
  • Partnered with CERN's HLS4ML team to implement feature enhancements and optimizations.
Relevant Coursework
Principles of Computer Architecture Parallel Computer Architecture Parallel Computation Parallel Computation in Bioinformatics Design Automation and Prototyping Validation and Testing in Embedded Systems Algorithms in Computational Biology Computational Evolutionary Biology
Languages

English (fluent)  ·  Hindi (native)  ·  Bengali (fluent)